The present invention relates to memory circuits, and more specifically, to sense amplifiers for SRAM (Static Random Access Memory).
Consider a computer system, such as that illustrated in FIG. 1. In FIG. 1, microprocessor die 102 comprises many sub-blocks, such as arithmetic logic unit (ALU) 104 and on-die cache 106. Microprocessor 102 may also communicate to other levels of cache, such as off-die cache 108. Higher memory hierarchy levels, such as system memory 110, are accessed via host bus 112 and chipset 114. In addition, other off-die functional units, such as graphics accelerator 116 and network interface controller (NIC) 118, to name just a few, may communicate with microprocessor 102 via appropriate busses or ports.
Advanced microprocessors use large SRAM (Static Random Access Memory)caches with fast read/write operations to store data and instructions. Other components in the computer system of FIG. 1 may also use SRAM to store data. The bit of information stored within a memory cell of a SRAM is read by sensing the voltage developed on two complementary bitlines. An example of a sense amplifier for sensing the bitline voltages is provided in FIG. 2. Complementary bitlines 202 and 204 are connected to the sense amplifier by column-select transistors 206 and 208. These column-select transistors are turned ON by driving column-select line 210 LOW. Before a read operation is performed, pre-charge line 212 is driven LOW so that pMOSFETs 214, 216, and 218 charge bitlines 202 and 204 to VDD (HIGH). Transistors 220, 222, 224, and 226 are cross-coupled inverters, which are enabled by driving enable line 228 HIGH.
After pre-charge, when the column-select transistors are ON and the cross-coupled inverters are enabled, the selected memory cell will discharge one of the two complementary bitlines such that the pMOSFET in one of the two cross-coupled inverters switches ON, whereupon the cross-coupled inverters latch the data read from the selected memory cell.
The above may be explained in more detail as follows. Suppose the data stored in the memory cell is such that during a read operation, bitline 202 stays HIGH and bitline 204 goes LOW. Initially, both bitlines are pre-charged HIGH, pMOSFET 230 is ON, nMOSFETs 222 and 226 are ON and their sources and drains are HIGH, and pMOSFETs 220 and 224 are OFF. After pre-charge, pre-charge line 212 is driven HIGH, an enable line 228 is driven HIGH so that pMOSFET 230 switches OFF and nMOSFET 232 switches ON. Current will flow though bitline 202 from a HIGH (VDD) potential to a LOW (VSS) potential through nMOSFETs 222 and 232 for some time interval. The charge stored by the total capacitance connected to node 234 is discharged via bitline 204 to the memory cell and also the path comprising nMOSFET 226 and 232. Eventually node 234 is discharged to the point where pMOSFET 220 starts to switch ON and nMOSFET 222 starts to switch OFF. Bitline 204 will continue to discharge LOW.
As discussed above, there is some portion of time for which current flows from the VDD potential to the VSS potential through bitline 202. This results in wasted power. Also, a sufficient amount of charge must be dumped to ground so that node 234 is brought to the point where pMOSFET 220 starts to switch ON and nMOSFET 222 starts to switch OFF. In practice, to multiplex multiple bitlines to the sense amplifier, there will be multiple column-select pMOSFETs of the type pMOSFET 204 connected to node 234 which contributes to the total capacitance seen by node 234. As this total capacitance increases, the evaluation time also increases, thereby slowing down the read operation.
In high performance microprocessors, it is desirable for caches to waste as little energy as possible during a read operation, and for the read operation to be fast.